Networked and Embedded Systems Laboratory

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Abstract

Interconnects have been shown to be a dominant source of energy
consumption in modern day System-on-Chip (SoC) designs. With
a large (and growing) number of electronic systems being designed
with battery considerations in mind, minimizing the energy consumed
in on-chip interconnects becomes crucial. Further, the use
of nanometer technologies is making it increasingly important to
consider reliability issues during the design of SoC communication
architectures. Continued supply voltage scaling has led to decreased
noise margins, making interconnects more susceptible to
noise sources such as crosstalk, power supply noise, radiation induced
defects, etc. The resulting transient faults cause the interconnect
to behave as an unreliable transport medium for data signals.
Therefore, fault tolerant communication mechanisms, such as Automatic
Repeat Request (ARQ), Forward Error Correction (FEC),
etc., which have been widely used in the networking community,
are likely to percolate to the SoC domain.
This paper presents a survey of techniques for energy efficient
on-chip communication. Techniques operating at different levels
of the communication design hierarchy are described, including
circuit-level techniques, such as low voltage signaling, architecture level
techniques, such as communication architecture selection and
bus isolation, system-level techniques, such as communication based
power management and dynamic voltage scaling for interconnects,
and network-level techniques, such as error resilient encoding for
packetized on-chip communication. Emerging technologies, such
as Code Division Multiple Access (CDMA) based buses, and wireless
interconnects are also surveyed.

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