Networked and Embedded Systems Laboratory

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With recent improvements in the energy efficiency of digital microprocessors and radio transceivers, the relative contribution of the analog front end in the overall power consumption of a wireless health system has been steadily rising. A key reason for this is that sampling rates in most medical applications are extremely low, providing opportunities to aggressively duty cycle the power hungry processor and radio. Analog front ends have not traditionally been duty cycled because analog filters with large time constants dictate a prohibitively high wake up latency. In this paper, we show that this latency can be reduced to a large extent and duty cycling made feasible by making filters “remember” their state across power gating cycles. This is done using slight hardware modifications that can even be applied to existing boards. We illustrate our technique on a commercially available wireless electro-cardiography system. Using our methodology, we reduced the restart delay of the circuit by three orders of magnitude from 6s to 5ms. We employ our circuit design for energy efficient QRS complex detection and extraction, which results in a 3× reduction in analog front end energy consumption.

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